Logic element

ABSTRACT

A digital logic element in which a single voltage supply provided current to an input circuit connected in series with a diode biased in the forward conduction region. Voltage for supplying part of a digital output circuit in the element is taken from the junction of the input circuit and the diodes.

United States Patent I72] Inventors I'lansllofimann l'larks-l'leide;

2,945,221 7 1960 Hint0n....... 2,989,235 6 1961 Dickinson..... 3,425,053 1/1969 Anderson.....................

Ludwig Wittorl, Harks-Heide; Hans- .Wilhelm Neuhaus, Hamburg; Uwe Bertram, Hamburg, all of, Germany [2|] Appl. No. 802,576 [22] Filed Feb. 26, I969 [45] Patented Aug. 24, I971 [73] Assignee U. S. Philips Corporation Primary Examiner-Donald D. Forrer New York, N.Y. Feb. 29, 1968 Germany Assistant Examiner-David M. Carter A1torneyFrank R. Trifari 32 Priority 1311 1 15 37 986.9

[54] LOGIC ELEMENT 4 Claims, 2 Drawing Figs. [52] ABSTRACT: A digital logic element in which a single voltage supply provided current to an input circuit connected in series egion. Voltage the element is f the input circuit and the diodes.

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INVENTORJ UWE IERTRAM av t- LOGIC ELEMENT The invention relates to a logic element for use in logic element systems which have predetermined supply and signal voltages and include at least one input and one output circuit. In many known logic elements a logic input signal is frequently used several times, the control stage which delivers the logic signal having to be protected from being overloaded. The inverse of the logic signal often also is to be applied and this may,

in many cases result in the number of input terminals of the logic element being insufficient so that one must forego the application of the inverse of the logic input signal. This results in that frequently additional inverters are required before the desired logic interconnection proper can be made. This has the drawback that the transit time of the logic element is unnecessarily increased, the term transit time being defined as the time which elapses between the application of an input signal and the appearance of an output signal at an output of the logic element. This transit time may be shortened by reducing the resistivity both of the inverters and of the parts of the elements in which the logic interconnection proper takes place. However, a narrow limit is set tothis decrease which is determined by the maximum permissible dissipation of the housing accommodating the logic element. A reduction of the supply voltage would solve this problem, but this generally is not permitted.

Circuit arrangements are known which operate according to the current transfer principle (Emitter Coupled Logic) and which make logic connections by means of series and parallel connected current switches. These circuit arrangements have the disadvantages, however, that they can only be adapted to logic elements designed according to a different technique, (for example, Diode Transistor Logic or Transistor Transistor Logic) by the use of an additional supply voltage. Furthermore, in these arrangements only the current required for effecting a single logic connection is switched. Hence this current cannot be used to make other logic connections.

It is an object of the present invention to provide a logic element which does not have the above disadvantages, and the invention is characterized in that at least part of the input circuit and at least part of the output circuit are connected in se ries with the voltage supply source, means being provided to ensure that the intermediate voltage set up at the junction point of the said parts of the input and output circuits is maintained constant irrespective of the logic condition of the logic element. l

Features and advantages of the invention will appear from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 shows schematically an embodiment of a logic element in accordance with the invention,

FIG. 2 is the truth table of the logic element shown in FIG. 1.

Referring to FIG. I, the logic element E shown is a binaryto-decimal code converter having four signal inputs A,, B',, C, and D, and 10 signal outputs to 9. The element E shown in FIG. 1 comprises four input circuit A,,, B C and D which are connected to the inputs A,, 8,, C, and D,, respectively. Each of the signal outputs 0 to 9 is connected to an output circuit. For the sake of clarity, only the output circuit associated with the signal output is shown completely. The output circuits associated with the other signal output are of identical structure. From FIG. 1 it will be easily seen that the input circuit A and the inverter stage T, of the output circuit are connected in series with the voltage supply source U, and that the voltage at the junction of the input and output circuits is maintained constant by means of diodes D and D The input circuit A B C and D each comprise two transistors T and T, operating as inverters, the emitters of these transistors being connected to the supply points x,,, x,, x, and x, of the respective input circuit. In the input circuit A the base of the transistor T is connected through a semiconductor diode D, to the signal input A, and also through a resistor R, to the supply point z, of the input circuit A,,. The collector of the transistor T is connected to the base of the transistor T through the emitter collector path of the transistor T, operating as a switch. The doubly inverted logic signal A is taken from the collector of the transistor T and the inverted logic signal A is taken from the collector of the transistor T The supply points z,,, 12 and 13 of the respective input circuits A,,, B C and D are connected to a supply terminal Z of the logic element which is connected to the voltage supply source U,,. The supply point x,,, x,, x, and x are not at earth potential but are connected to earth through the diodes D and D This ensures that the threshold voltage for all four signal inputs A,, 8,, C, and D, is equal. In addition, in this manner two diodes and a base resistor are saved in each input circuit which normally are required to provide the threshold voltage.

The output circuit x includes an OR-gate which has the advantage that it can be accommodated in a single common island in an integrated circuit. It comprises transistors T,,, T-,, T, and T the collectors of which are connected to the supply point z, of the output circuit 2: The bases of the latter transistors constitute the signal inputs U,, U U and U, respectively of the output circuit A7 The emitters of these transistors are connected through the series combination of the resistors R and R to the supply point x, of the output circuit x which supply point is connected to the supply terminal Y of the logic element, which terminal is connected to earth. The junction point of the resistors R and R is connected to the base of the transistor T the collector of which is connected to the base of the transistor T The emitters of the transistors T, and T are connected to the supply point x, of the output circuit x,-,. The collector of the transistor T is con nected through the resistor R to the supply point z, of the output circuit x which point is connected to the supply terminal 1 of the logic element. The collector of the transistor T, is connected through the resistor R, to the supply point U,, of the output circuit x,-,, which supply point is connected to the junction of the supply points x,,, x,, x and x, of the input circuit. The output circuits associated with the other signal outputs are identical structure. All the supply points z, of the output circuit are connected to the supply terminal z of the logic element, all the supply points x, of the output circuits are connected to the supply terminal y of the logic element and all the supply points U,, of the output circuits are connected to the junction of the supply points x,,, x,, x and x, of the input circuits. Each of the signal inputs U,, U U and U, of each of the output circuits is connected to a signal output of one of the input circuits, which will be discussed more fully with reference to FIG. 2.

FIG. 2 is a truth table of a binary-to-decimal code converter. It is assumed that a logical l is distinguished from a logical 0 by a higher potential (positive logic). It is further assumed that in the embodiment described decoding is continued to 0, which means that at a given combination of the values of the input signals the logical 0 appears at the respective signal output. This means that all the functions shown in column I of the table are to be inverted, as is shown in column 2. The functions shown in column 2 can be achieved by means of a single OR-gate or by an AND-gate followed by an inverter. In the embodiment shown in FIG. 1, each output circuit includes an OR-gate (T T T and T,,) which is followed by a double inverter circuit (T T This double inverter circuit provides an increased load capacity of the signal outputs 0 to 9, whilst the contribution of the two inverters to the overall transit time is negligible. From column 2 ofthe truth table it can readily be read which input signals are to be applied to the signal inputs of each of the output circuits. Thus, for example, the signals A, D, C and D are applied to the signal inputs of the output circuit X If, therefore, the logical signals 1, 0, 1,0 are applied to the inputs A,, B,, C, and D, respectively, the logical signals 0, 0, 0, 0 are applied to the inputs of the output circuit X This implies that the transistors T,,, T,,, T-,, T, and T will be nonconducting and the transistor T will be conducting. Consequently, a logical appears at the output 5.

Since the first inverter stages (T of each of the output circuits at least nine transistors will be conducting and the sudden potential variations at the collectors of these transistors are very small (base-emitter voltage of T minus collectoremitter saturation voltage of T.,), a lower supply voltage U may advantageously be used for the transistors. As a result not only will the dissipation be considerably reduced, but also the resistors R in each of the output circuits may be made smaller, which especially in integrated circuits provides a considerably saving in crystal surface.

The division of the supply voltage as described with reference to the embodiments shown in FIG. 1 can be used in many other circuits. The principle described can be used both in circuits comprising discrete components and in integrated circuits.

What we claim is:

1. A logic element for use in a logic system having predetermined supply and signal voltages, comprising an input circuit, an output circuit and a voltage regulating circuit; said input circuit comprising an input terminal for receiving digital signals above and below a predetermined first voltage level, a first conduction path means connected to the input terminal for permitting current to flow therethrough in response to a voltage on the input terminal above a first voltage level and for preventing current from flowing therethrough in response to a voltage level on the input terminal below the first voltage level, a second conduction path means connected to the input terminal for permitting a current to flow therethrough in response to a voltage on the input terminal below the first voltage level and for preventing current from flowing therethrough in response to a voltage on the input terminal above the first voltage level, means for connecting one side of each conduction path means to the supply voltage of the logic system, and means for connecting the other sides of the conduction path means remote from the voltage supplied to a single point; said voltage regulating circuit comprising means for maintaining a constant voltage across the regulating circuit in response to variable currents passing therethrough; means for connecting the regulating circuit between the single point and ground; and means for connecting a part of the output circuit parallel with the regulating circuit.

2. A logic circuit as claimed in claim 1, wherein the voltage maintained by the regulating circuit is approximately equal to the first voltage level.

3. A logic circuit as claimed in claim 1, wherein the regulating circuit comprises a constantly forward biased diode.

4. A logic circuit as claimed in claim 1, wherein the entire logic circuit is integrated in a semiconductor circuit. 

1. A logic element for use in a logic system having predetermined supply and signal voltages, comprising an input circuit, an output circuit and a voltage regulating circuit; said input circuit comprising an input terminal for receiving digital signals above and below a predetermined first voltage level, a first conduction path means connected to the input terminal for permitting current to flow therethrough in response to a voltage on the input terminal above a first voltage level and for preventing current from flowing therethrough in response to a voltage level on the input terminal below the first voltage level, a second conduction path means connected to the input terminal for permitting a current to flow therethrough in response to a voltage on the input terminal below the first voltage level and for preventing current from flowing therethrough in response to a voltage on the input terminal above the first voltage level, means for connecting one side of each conduction path means to the supply voltage of the logic system, and means for connecting the other sides of the conduction path means remote from the voltage supplied to a single point; said voltage regulating circuit comprising means for maintaining a constant voltage across the regulating circuit in response to variable currents passing therethrough; means for connecting the regulating circuit between the single point and ground; and means for connecting a part of the output circuit parallel with the regulating circuit.
 2. A logic circuit as claimed in claim 1, wherein the voltage maintained by the regulating circuit is approximately equal to the first voltage level.
 3. A logic circuit as claimed in claim 1, wherein the regulating circuit comprises a constantly forward biased diode.
 4. A logic circuit as claimed in claim 1, wherein the entire logic circuit is integrated in a semiconductor circuit. 